HD64F38602R Datasheet, PDF (386/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 17 A/D Converter
17.4.3
Operating States of A/D Converter
Table 17.2 shows the operating states of the A/D converter.
Table 17.2 Operating States of A/D Converter
Operating
Mode
Reset
Active Sleep
Watch
Sub-
active
Module
Sub-sleep Standby Standby
AMR
Reset
Functions Retained
Retained
Functions/ Retained
Retained*²
Retained
Retained
ADSR
Reset
Functions Functions Retained
Functions/ Functions/ Retained
Retained*² Retained*²
Retained
ADRR
Retained*¹ Functions Functions Retained
Functions/ Functions/ Retained
Retained*² Retained*²
Retained
Notes: 1. Undefined at a power-on reset.
2. Function if φw/2 is selected as the internal clock. Halted and retained otherwise.
17.5 Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 17.3 shows the operation timing.
1. Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the
analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D
conversion is started by setting bit ADSF to 1.
2. When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRR. At the same time bit ADSF is cleared to 0, and the A/D converter goes to the
idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Rev. 3.00 May 15, 2007 Page 354 of 516
REJ09B0152-0300