HD64F38602R Datasheet, PDF (142/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 6 ROM
8. The maximum number of repetitions of the programming/programming-verifying sequence of
the same bit is 1,000.
Write pulse application subroutine
Apply Write Pulse
Enable WDT
Set PSU bit to 1
Wait 50 µs
*
Set P bit to 1
Wait (Wait time = programming time)
Clear P bit to 0
START
Set SWE bit to 1
Wait 1 µs
Store 128-byte programming data in programming
data area and reprogramming data area
n=1
m=0
Write 128-byte reprogramming data in RAM
consecutively to flash memory
Wait 5 µs
Clear PSU bit to 0
Wait 5 µs
Disable WDT
Apply Write pulse
Set PV bit to 1
Wait 4 µs
Set block start address as
verifying address
End Sub
Dummy write H'FF to verifying address
Wait 2 µs
*
Read verifying data
Increment address
Verifying data =
No
write data?
Yes
n≤6?
No
Yes
Additional-programming data computation
m=1
Reprogramming data computation
n←n+1
128-byte of
No
data verified?
Yes
Clear PV bit to 0
Wait 2 µs
n ≤ 6?
No
Yes
Write 128-byte additional-programming data
in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m=0?
No
Yes
Clear SWE bit to 0
Wait 100 µs
End of programming
n ≤ 1000 ? ^Yes
No
Clear SWE bit to 0
Wait 100 µs
Programming failure
Note: * The RTS instruction must not be used during the following periods.
1. A period from programming 128-byte data to flash memory until clearing the P bit
2. A period from dummy-writing of H'FF to a verifying address until reading verifying data
Figure 6.3 Program/Program-Verify Flowchart
Rev. 3.00 May 15, 2007 Page 110 of 516
REJ09B0152-0300