HD64F38602R Datasheet, PDF (135/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 6 ROM
6.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the erase block of flash memory. EBR1 is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be
automatically cleared to 0.
Bit
7 to 5
Initial
Bit Name Value

All 0
4
EB4
0
3
EB3
0
2
EB2
0
1
EB1
0
0
EB0
0
R/W

R/W
R/W
R/W
R/W
R/W
Description
Reserved
Although these bits are readable/writable, only 0 should
be written to.
When this bit is set to 1, a12-Kbyte area of H'1000 to
H'3FFF will be erased.
When this bit is set to 1, a 1-Kbyte area of H'0C00 to
H'0FFF will be erased.
When this bit is set to 1, a 1-Kbyte area of H'0800 to
H'0BFF will be erased.
When this bit is set to 1, a 1-Kbyte area of H'0400 to
H'07FF will be erased.
When this bit is set to 1, a 1-Kbyte area of H'0000 to
H'03FF will be erased.
6.2.4 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when this LSI
enters the subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Initial
Bit
Bit Name Value
7
PDWND 0
6 to 0 
All 0
R/W
R/W

Description
Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to subactive
mode.
Reserved
These bits are always read as 0.
Rev. 3.00 May 15, 2007 Page 103 of 518
REJ09B0152-0300