HD64F38602R Datasheet, PDF (112/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
5.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit Bit Name
7 to 5 
4
NESEL
3
DTON
2
MSON
1
SA1
0
SA0
Initial
Value R/W
All 1 
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φ ) and the system clock pulse generator
W
generates the oscillator clock (φ ). This bit selects the
OSC
sampling frequency of φ when φ is sampled. When a
OSC
W
system clock is used, clear this bit to 0.When the on-
chip oscillator is selected, set this bit to 1.
0: Sampling rate is φ_OSC/16.
1: Sampling rate is φ /4.
OSC
Direct Transfer on Flag
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY,
TMA3, and LSON in SYSCR1 and bit MSON in
SYSCR2. For details, see table 5.2.
Medium Speed on Flag
After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed)
mode.
0: Operation in active (high-speed) mode
1: Operation in active (medium-speed) mode
Subactive Mode Clock Select 1 and 0
Select the operating clock frequency in subactive and
subsleep modes. The operating clock frequency
changes to the set frequency after the SLEEP
instruction is executed.
00: φ /8
W
01: φ /4
W
10: φ_W/2
11: φ
W
Rev. 3.00 May 15, 2007 Page 80 of 516
REJ09B0152-0300