HD64F38602R Datasheet, PDF (73/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
Section 3 Exception Handling
Exception handling is caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts after the reset state is
cleared by a negation of the RES signal. Exception handling is also started when the watchdog
timer overflows. The exception handling executed at this time is the same as that for a reset by
the RES pin.
• Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. A vector address
corresponding to a vector number from 0 to 3 which are specified in the instruction code is
generated. Exception handling can be executed at all times in the program execution state,
regardless of the setting of the I bit in CCR.
• Interrupts
External interrupts other than the NMI and internal interrupts are masked by the I bit in CCR,
and kept pending while the I bit is set to 1. Exception handling starts when the current
instruction or exception handling ends, if an interrupt is requested.
Rev. 3.00 May 15, 2007 Page 41 of 516
REJ09B0152-0300