HD64F38602R Datasheet, PDF (144/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 6 ROM
6.4.2 Erasing/Erasing-Verifying
When erasing flash memory, the erasing/erasing-verifying flowchart shown in figure 6.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasure is performed in block units. Select a single block to be erased through erase block
register 1 (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erasing time.
4. The watchdog timer (WDT) is set to prevent the flash memory overerasing due to program
crush, etc. An overflow cycle of approximately 19.8 ms is adequate.
5. For writing dummy data to a verifying address, write one byte of data H'FF to an address
whose lower two bits are B'00. Verifying data can be read in longwords from the address to
which a dummy data is written.
6. If the read data is not erased successfully, set erasing mode again, and repeat the
erasing/erasing-verifying sequence as before. The maximum number of repetitions of the
erase/erase-verify sequence is 100.
6.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts including the NMI interrupt are disabled while flash memory is being programmed
or erased or while the boot program is executed for the following three reasons.
1. An interrupt during programming/erasure may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before programming the vector address or during
programming/erasure, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
Rev. 3.00 May 15, 2007 Page 112 of 516
REJ09B0152-0300