HD64F38602R Datasheet, PDF (540/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
14.8.2 Mark State and Break
Sending
Section 16 I2C Bus Interface 2
(IIC2)
16.3.5 I²C Bus Status Register
(ICSR)
Page Revisions (See Manual for Details)
277 Modified
When the SPC3 bit in SPCR is 0, the TXD3 pin
functions as an I/O port whose direction (input or
output) and level are determined by PCR and PDR,
regardless of the TE setting. This can be used to set the
TXD3 pin to the mark state (high level) or send a break
during data transmission. To maintain the
communication line at the mark state until the SPC3 bit
in SPCR is set to 1, set both PCR and PDR to 1. As the
SPC3 bit in SPCR is cleared to 0 at this point, the TXD3
pin functions as an I/O port, and 1 is output from the
TXD3 pin. To send a break during data transmission,
first set PCR to 1 and PDR to 0, and then clear the
SPC3 and TE bits to 0. When the TE bit is cleared to 0
directly after the SPC3 bit is cleared to 0, the transmitter
is initialized regardless of the current transmission state
after the TE bit is cleared, the TXD3 pin functions as an
I/O port after the SPC3 bit is cleared, and 0 is output
from the TXD3 pin.
323 Modified
Bit
Bit Name Description
3
STOP
Stop Condition Detection Flag[Setting
conditions]
• In master mode, when a stop condition
is detected after the completion of
frame transfer
• In slave mode, when a stop condition is
detected, after the slave address of the
first byte, following the general call and
the detection of the start condition,
matches the address set in SAR
Rev. 3.00 May 15, 2007 Page 508 of 516
REJ09B0152-0300