HD64F38602R Datasheet, PDF (211/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
10.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Figure 10.21 shows the timing of the IMFA to IMFD flag setting at compare match.
φ
TCNT input
clock
TCNT
N
N+1
GRA to GRD
N
Compare
match signal
IMFA to IMFD
IRRTW
Figure 10.21 Timing of IMFA to IMFD Flag Setting at Compare Match
Rev. 3.00 May 15, 2007 Page 179 of 518
REJ09B0152-0300