HD64F38602R Datasheet, PDF (334/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
Serial Data Transmission and Reception: Data transmission and reception is a combined
operation of data transmission and reception which are described before. Transmission and
reception is started by writing data in SSTDR. When the eighth clock rises or the ORER bit is set
to 1 while the TDRE bit is set to 1, transmission and reception is stopped.
To switch from transmit mode (TE = 1) or receive mode (RE = 1) to transmit and receive mode
(TE = RE = 1), the TE and RE bits should be cleared to 0. After confirming that the TEND,
RDRF, and ORER bits are cleared to 0, set the TE and RE bits to 1.
Figure 15.9 shows a sample flowchart for serial transmit and receive operations.
Start
Initialization
[1]
Read TDRE in SSSR
No
TDRE = 1?
Yes
Write transmit data
in SSTDR
[1] After reading SSSR and confirming that
the TDRE bit is 1, write transmit data in
SSTDR. Then the TDRE bit is automatically
cleared to 0.
[2]
No
Read RDRF in SSSR
RDRF = 1?
Yes
Read receive data
in SSRDR
[2] Confirm that the RDRF bit is 1. If the RDRF
bit is 1, receive data in SSRDR is read. If the
SSRDR bit is read, the RDRF bit is automatically
cleared.
[3]
Data transmission
Yes
continued?
No
Clear TEND to 0 and
[4]
clear TE and RE in
SSER to 0
End
[3] Determine whether data transmission is continued.
[4] To end transmit and receive mode, clear the
TEND bit to 0 and clear the TE and RE bits in
SSER to 0.
Figure 15.9 Sample Flowchart for Serial Transmit and Receive Operations
Rev. 3.00 May 15, 2007 Page 302 of 516
REJ09B0152-0300