HD64F38602R Datasheet, PDF (312/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.8.7
Relation between RDR Reading and bit RDRF
In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0
when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is
read more than once, the second and subsequent read operations will be performed while bit
RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0,
if the read operation coincides with completion of reception of a frame, the next frame of data may
be read. This is shown in figure 14.19.
Frame 1
Frame 2
Frame 3
Communication line
Data 1
Data 2
Data 3
RDRF
RDR
Data 1
Data 2
RDR read
(A) (B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 14.19 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To be
precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clock
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
Rev. 3.00 May 15, 2007 Page 280 of 516
REJ09B0152-0300