HD64F38602R Datasheet, PDF (342/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.11 Interrupt Requests
The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun
error, and conflict error. Since these interrupt requests are assigned to the common vector address,
interrupt sources must be determined by flags. Table 15.3 lists the interrupt requests.
Table 15.3 Interrupt Requests
Interrupt Request
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
Abbreviation
TXI
TEI
RXI
OEI
CEI
Interrupt Condition
(TIE = 1), (TDRE = 1)
(TEIE = 1), (TEND = 1)
(RIE = 1), (RDRF = 1)
(RIE = 1), (ORER = 1)
(CEIE = 1), (CE = 1)
When an interrupt condition shown in table 15.3 is 1 and the I bit in CCR is 0, the CPU executes
the interrupt exception handling. Each interrupt source must be cleared during the exception
handling. Note that the TDRE and TEND bits are automatically cleared by writing transmit data in
SSTDR and the RDRF bit is automatically cleared by reading SSRDR. When transmit data is
written in SSTDR, the TDRE bit is set again at the same time. Then if the TDRE bit is cleared,
additional one byte of data may be transmitted.
15.5 Usage Note
When writing 1 to the SOLP bit in SSCRH (to enable write protect) after writing 0 to it (to disable
write protect), the SOL bit may be changed without being protected.
To avoid this, before writing 1 to the SOLP bit (to enable write protect), write the current value of
the SOL bit to itself. With this procedure, the write protect can be performed on the SOL bit.
Rev. 3.00 May 15, 2007 Page 310 of 516
REJ09B0152-0300