HD64F38602R Datasheet, PDF (341/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
15.4.10 SCS Pin Control and Arbitration
When the SSUMS bit in SSCRL is set to 1 and the CSS1 bit in SSCRH is set to 1, the MSS bit in
SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer.
If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in
SSSR is set and the MSS bit is cleared.
Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the
CE bit must be cleared to 0 before starting transmission.
When the multimaster error is used, the CSOS bit in SSCRL should be set to 1.
SCS input
Internal SCS
(synchronized)
MSS
Transfer start
Write data
in SSTDR
CE
SCS output
(Hi-Z)
Arbitration detection
period
Maximum time of SCS internal synchronization
Figure 15.13 Arbitration Check Timing
Rev. 3.00 May 15, 2007 Page 309 of 518
REJ09B0152-0300