HD64F38602R Datasheet, PDF (541/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
Figure 16.15 Receive Mode
Operation Timing
Section 17 A/D Converter
17.3.1 A/D Result Register
(ADRR)
17.7.3 Usage Notes
Page Revisions (See Manual for Details)
339 Modified
SCL
SDA
(Input)
MST
7
8
1
2
Bit 6 Bit 7 Bit 0 Bit 1
TRS
RDRF
ICDRS
Data 2
Data 3
ICDRR
Data 1
Data 2
User
processing
[3]Read ICDRR
350 Modified
ADRR is a 16-bit read-only register that stores the
results of A/D conversion. The data is stored in the
upper 10 bits of ADRR. ADRR can be read by the CPU
at any time, …
360 Deleted
3. When A/D conversion is started after clearing module
standby mode, wait for 10φ clock cycles before
starting A/D conversion.
4. When the LADS bit in ADSR is changed as from
halting to operating, wait for 10φ clock cycles before
starting A/D conversion.
Rev. 3.00 May 15, 2007 Page 509 of 516
REJ09B0152-0300