HD64F38602R Datasheet, PDF (258/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
Figure 13.4 and table 13.2 show examples of event counter PWM operation.
toff = T × (Ndr +1)
ton
tcm = T × (Ncm +1)
ton: Clock input enable time
toff: Clock input disable time
tcm: One conversion period
T: ECPWM input clock cycle
Ndr: Value of ECPWDR
Ncm: Value of ECPWCR
Figure 13.4 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this
condition, event counter PWM output (IECPWM) is fixed low.
Table 13.2 Examples of Event Counter PWM Operation
Conditions:
f_OSC = 4 MHz, fφ = 4 MHz, f_W = 32.768 kHz, fφ_W = 32.768 kHz, high-speed
active mode, ECPWCR value (Ncm) = H'7A11, ECPWDR value (Ndr) = H'16E3
Clock
Source
Selection
Clock
Source
Cycle (T)*
ECPWCR Value
(Ncm)
ECPWDR
Value (Ndr)
toff = T × (Ndr
+ 1)
tcm = T × (Ncm ton = tcm –
+ 1)
toff
φ/2
0.5 µs
H'7A11
H'16E3
2.93 ms
15.625 ms
12.695 ms
φ/4
1 µs
D'31249
D'5859
5.86 ms
31.25 ms
25.39 ms
φ/8
2 µs
11.72 ms
62.5 ms
50.78 ms
φ/16
4 µs
23.44 ms
125.0 ms
101.56 ms
φ/32
8 µs
46.88 ms
250.0 ms
203.12 ms
φ/64
16 µs
93.76 ms
500.0 ms
406.24 ms
φ_W/16
488 µs
Note: * toff minimum width
2861.59 ms 15260.19 ms 12398.60 ms
Rev. 3.00 May 15, 2007 Page 226 of 516
REJ09B0152-0300