HD64F38602R Datasheet, PDF (358/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
Initial
Bit Bit Name Value R/W Description
0
ADZ
0
R/(W)* General Call Address Recognition Flag
This bit is valid in I²C bus format slave receive mode.
[Setting condition]
• When the general call address is detected in slave
receive mode
[Clearing condition]
• When 0 is written in ADZ after reading ADZ = 1
Note: * Only 0 can be written to clear the flag.
16.3.6 Slave Address Register (SAR)
SAR selects the communication format and sets the slave address. When the chip is in slave mode
with the I²C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame
received after a start condition, the chip operates as the slave device.
Bit
7 to 1
Bit Name
SVA6 to
SVA0
0
FS
Initial
Value R/W Description
All 0 R/W Slave Address 6 to 0
These bits set a unique address in bits SVA6 to SVA0,
differing form the addresses of other slave devices
connected to the I²C bus.
0
R/W Format Select
0: I²C bus format is selected.
1: Clock synchronous serial format is selected.
16.3.7
I²C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT during
transferring data of ICDRS, continuous transfer is possible. If the MLS bit of ICMR is set to 1
and when the data is written to ICDRT, the MSB/LSB inverted data is read. The initial value of
ICDRT is H'FF. The initial value of ICDRT is H'FF.
Rev. 3.00 May 15, 2007 Page 326 of 516
REJ09B0152-0300