HD64F38602R Datasheet, PDF (268/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Initial
Bit
Bit Name Value R/W Description
4
PM
0
R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
When even parity is selected, a parity bit is added in
transmission so that the total number of 1 bits in the
transmit data plus the parity bit is an even number, in
reception, a check is carried out to confirm that the
number of 1 bits in the receive data plus the parity bit is
an even number.
When odd parity is selected, a parity bit is added in
transmission so that the total number of 1 bits in the
transmit data plus the parity bit is an odd number, in
reception, a check is carried out to confirm that the
number of 1bits in the receive data plus the parity bit is
an odd number.
If parity bit addition and checking is disabled in clock
synchronous mode and asynchronous mode, the PM bit
setting is invalid.
3
STOP
0
R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit
is 0, it is treated as the start bit of the next transmit
character.
2
MP
0
R/W 5-Bit Communication
When this bit is set to 1, the 5-bit communication format
is enabled. Make sure to set bit 5 (PF) to 1 when setting
this bit (MP) to 1.
Rev. 3.00 May 15, 2007 Page 236 of 516
REJ09B0152-0300