HD64F38602R Datasheet, PDF (272/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.7 Serial Status Register (SSR)
SSR consists of status flags of the SCI3. 1 cannot be written to flags TDRE, RDRF, OER, PER,
and FER; they can only be cleared.
SSR is initialized to H'84 by a reset or in standby mode, watch mode, or module standby mode.
Initial
Bit
Bit Name Value R/W Description
7
TDRE
1
R/(W)* Transmit Data Register Empty
Indicates that transmit data is stored in TDR.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
6
RDRF
0
R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive
data is transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
When data is read from RDR
If an error is detected in reception, or if the RE bit in
SCR has been cleared to 0, RDR and bit RDRF are not
affected and retain their previous state.
Note that if data reception is completed while bit RDRF
is still set to 1, an overrun error (OER) will occur and
the receive data will be lost.
Rev. 3.00 May 15, 2007 Page 240 of 516
REJ09B0152-0300