HD64F38602R Datasheet, PDF (300/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.5.4
Serial Data Reception (Clock Synchronous Mode)
Figure 14.12 shows an example of SCI3 operation for reception in clock synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronous clock input or
output, starts receiving data.
2. The SCI3 stores the received data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI3 interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is
generated.
Serial
clock
Serial
data
RDRF
Bit 7
Bit 0
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
1 frame
Bit 7
OER
LSI
operation
User
processing
RXI3
interrupt
request
generated
RDRF flag
cleared
to 0
RDR data read
RXI3 interrupt
request generated
RDR data has
not been read
(RDRF = 1)
ERI3 interrupt request
generated by
overrun error
Overrun error
processing
Figure 14.12 Example of SCI3 Reception Operation in Clock Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.13 shows a sample flowchart
for serial data reception.
Rev. 3.00 May 15, 2007 Page 268 of 516
REJ09B0152-0300