HD64F38602R Datasheet, PDF (15/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.2 Register Descriptions ......................................................................................................... 202
12.2.1 Timer Control/Status Register WD1 (TCSRWD1)............................................... 203
12.2.2 Timer Control/Status Register WD2 (TCSRWD2)............................................... 205
12.2.3 Timer Counter WD (TCWD)................................................................................ 206
12.2.4 Timer Mode Register WD (TMWD) .................................................................... 207
12.3 Operation ........................................................................................................................... 208
12.3.1 Watchdog Timer Mode ......................................................................................... 208
12.3.2 Interval Timer Mode............................................................................................. 209
12.3.3 Timing of Overflow Flag (OVF) Setting .............................................................. 209
12.4 Interrupt ............................................................................................................................. 210
12.5 Usage Notes ....................................................................................................................... 210
12.5.1 Switching between Watchdog Timer Mode and Interval Timer Mode................. 210
12.5.2 Module Standby Mode Control............................................................................. 210
12.5.3 Clearing the WT/IT or IEOVF Bit in TCSRWD2 to 0 ......................................... 210
Section 13 Asynchronous Event Counter (AEC) ..............................................213
13.1 Features.............................................................................................................................. 213
13.2 Input/Output Pins ............................................................................................................... 215
13.3 Register Descriptions ......................................................................................................... 215
13.3.1 Event Counter PWM Compare Register (ECPWCR) ........................................... 216
13.3.2 Event Counter PWM Data Register (ECPWDR).................................................. 217
13.3.3 Input Pin Edge Select Register (AEGSR)............................................................. 218
13.3.4 Event Counter Control Register (ECCR).............................................................. 219
13.3.5 Event Counter Control/Status Register (ECCSR)................................................. 220
13.3.6 Event Counter H (ECH)........................................................................................ 222
13.3.7 Event Counter L (ECL)......................................................................................... 222
13.4 Operation ........................................................................................................................... 223
13.4.1 16-Bit Counter Operation ..................................................................................... 223
13.4.2 8-Bit Counter Operation ....................................................................................... 224
13.4.3 IRQAEC Operation............................................................................................... 225
13.4.4 Event Counter PWM Operation............................................................................ 225
13.4.5 Operation of Clock Input Enable/Disable Function.............................................. 227
13.5 Operating States of Asynchronous Event Counter............................................................. 228
13.6 Usage Notes ....................................................................................................................... 229
Section 14 Serial Communication Interface 3 (SCI3, IrDA).............................231
14.1 Features.............................................................................................................................. 231
14.2 Input/Output Pins ............................................................................................................... 233
14.3 Register Descriptions ......................................................................................................... 233
14.3.1 Receive Shift Register (RSR) ............................................................................... 234
Rev. 3.00 May 15, 2007 Page xv of xxxii