HD64F38602R Datasheet, PDF (274/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
Initial
Bit
Bit Name Value R/W Description
3
PER
0
R/(W)* Parity Error
[Setting condition]
• When a parity error is generated during reception
[Clearing condition]
• When 0 is written to PER after reading PER = 1
When bit RE in SCR is cleared to 0, bit PER is not
affected and retains its previous state.
• Receive data in which a parity error has occurred is
still transferred to RDR, but bit RDRF is not set.
Reception cannot be continued with bit PER set to
1. In clock synchronous mode, neither transmission
nor reception is possible when bit PER is set to 1.
2
TEND
1
R
Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
1
MPBR
0
R
Reserved
This bit is always read as 0 and cannot be modified.
0
MPBT
0
R/W Reserved
The write value should always be 0.
Note: * Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 242 of 516
REJ09B0152-0300