HD64F38602R Datasheet, PDF (199/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
Periodic counting operation can be performed when GRA is set as an output compare register and
CCLR bit in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the
IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt
request is generated. TCNT continues counting from H'0000. Figure 10.3 shows periodic
counting.
TCNT value
GRA
H'0000
CTS bit
IMFA
Flag cleared
by software
Time
Figure 10.3 Periodic Counter Operation
By setting a general register as an output compare register, compare match A, B, C, or D can
cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle.
Figure 10.4 shows an example of 0 and 1 output when TCNT operates as a free-running counter, 1
output is selected for compare match A, and 0 output is selected for compare match B. When
signal is already at the selected output level, the signal level does not change at compare match.
TCNT value
H'FFFF
GRA
GRB
H'0000
FTIOA
FTIOB
No change
Time
No change
No change
No change
Figure 10.4 0 and 1 Output Example (TOA = 0, TOB = 1)
Rev. 3.00 May 15, 2007 Page 167 of 518
REJ09B0152-0300