HD64F38602R Datasheet, PDF (285/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.3.11 Serial Extended Mode Register (SEMR)
SEMR sets the basic clock used in asynchronous mode.
Bit
7 to 4
3
2 to 0
Initial
Bit Name Value R/W

All 0 
ABCS
0
R/W

All 0 
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Asynchronous Mode Basic Clock Select
Selects the basic clock for the bit period in
asynchronous mode.
This setting is enabled only in asynchronous mode
(COM bit in SMR3 is 0).
0: Operates on a basic clock with a frequency of 16
times the transfer rate
1: Operates on a basic clock with a frequency of eight
times the transfer rate
Clear the ABCS bit to 0, when the IrDA function is
enabled.
Reserved
These bits are always read as 0 and cannot be
modified.
14.4 Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling
edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a
frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.
When the ABCS bit in SEMR is 1, the data is sampled on the 4th pulse of a clock with a
frequency eight times the bit period. Inside the SCI3, the transmitter and receiver are independent
units, enabling full duplex. Both the transmitter and the receiver also have a double-buffered
structure, so data can be read or written during transmission or reception, enabling continuous data
transfer. Table 14.8 shows the 16 data transfer formats that can be set in asynchronous mode. The
format is selected by the settings in SMR as shown in table 14.9.
Rev. 3.00 May 15, 2007 Page 253 of 518
REJ09B0152-0300