HD64F38602R Datasheet, PDF (16/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.3.2 Receive Data Register (RDR)............................................................................... 234
14.3.3 Transmit Shift Register (TSR) .............................................................................. 234
14.3.4 Transmit Data Register (TDR).............................................................................. 234
14.3.5 Serial Mode Register (SMR) ................................................................................ 235
14.3.6 Serial Control Register (SCR) .............................................................................. 237
14.3.7 Serial Status Register (SSR) ................................................................................. 240
14.3.8 Bit Rate Register (BRR) ....................................................................................... 243
14.3.9 Serial Port Control Register (SPCR)..................................................................... 251
14.3.10 IrDA Control Register (IrCR)............................................................................... 252
14.3.11 Serial Extended Mode Register (SEMR) .............................................................. 253
14.4 Operation in Asynchronous Mode ..................................................................................... 253
14.4.1 Clock..................................................................................................................... 254
14.4.2 SCI3 Initialization................................................................................................. 258
14.4.3 Data Transmission ................................................................................................ 259
14.4.4 Serial Data Reception ........................................................................................... 261
14.5 Operation in Clock Synchronous Mode............................................................................. 265
14.5.1 Clock..................................................................................................................... 265
14.5.2 SCI3 Initialization................................................................................................. 265
14.5.3 Serial Data Transmission ...................................................................................... 266
14.5.4 Serial Data Reception (Clock Synchronous Mode) .............................................. 268
14.5.5 Simultaneous Serial Data Transmission and Reception........................................ 270
14.6 IrDA Operation .................................................................................................................. 271
14.6.1 Transmission......................................................................................................... 272
14.6.2 Reception .............................................................................................................. 273
14.6.3 High-Level Pulse Width Selection........................................................................ 273
14.7 Interrupt Requests .............................................................................................................. 274
14.8 Usage Notes ....................................................................................................................... 277
14.8.1 Break Detection and Processing ........................................................................... 277
14.8.2 Mark State and Break Sending ............................................................................. 277
14.8.3 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ......................................................................... 277
14.8.4 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ............................................................................................. 278
14.8.5 Note on Switching SCK3 Pin Function ................................................................ 279
14.8.6 Relation between Writing to TDR and Bit TDRE ................................................ 279
14.8.7 Relation between RDR Reading and bit RDRF.................................................... 280
14.8.8 Transmit and Receive Operations when Making State Transition........................ 281
14.8.9 Setting in Subactive or Subsleep Mode ................................................................ 281
14.8.10 Oscillator when Serial Communication Interface 3 is Used ................................. 281
Rev. 3.00 May 15, 2007 Page xvi of xxxii