HD64F38602R Datasheet, PDF (225/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 11 Realtime Clock (RTC)
11.3.7 Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by
the RUN bit in RTCCR1. When a clock other than φ_W/4 is selected, the RTC is disabled and
operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter,
RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to the
FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock
generated by dividing the system clock by 32, 16, 8, or 4 is output in active or sleep mode. φ_W is
output in active, sleep, subactive, subsleep, or watch mode.
Initial
Bit
Bit Name Value R/W Description
7
—
0
—
Reserved
This bit is always read as 0.
6
RCS6
0
R/W Clock Output Selection
5
RCS5
0
4
SUB32K 0
R/W Select a clock output from the TMOW pin when enabling
R/W ^{TMOW output in PMR1.}
000: φ/4
010: φ/8
100: φ/16
110: φ/32
3
RCS3
1
R/W
xx1: φ_W
Clock Source Selection
2
RCS2
0
R/W 0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1
RCS1
0
R/W 0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0
RCS0
0
R/W 0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1000: φ_W/4⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ RTC operation
1001 to 1111: Setting prohibited
Rev. 3.00 May 15, 2007 Page 193 of 518
REJ09B0152-0300