HD64F38602R Datasheet, PDF (315/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
Section 15 Synchronous Serial Communication Unit (SSU)
The synchronous serial communication unit (SSU) can handle clocked synchronous serial data
communication.
Figure 15.1 shows a block diagram of the SSU.
15.1 Features
• Can be operated in clocked synchronous communication mode or four-line bus communication
mode (including bidirectional communication mode)
• Can be operated as a master or a slave device
• Choice of eight internal clocks (φ/256, φ/128, φ/64, φ/32, φ/16, φ/8, φ/4, and φ_SUB/2) and an
external clock as a clock source
• Clock polarity and phase of SSCK can be selected
• Choice of data transfer direction (MSB-first or LSB-first)
• Receive error detection: overrun error
• Multimaster error detection: conflict error
• Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and
conflict error
• Continuous transmission and reception of serial data are enabled since both transmitter and
receiver have buffer structure
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The SSU is halted as the initial value. For details, refer to section 5.4, Module
Standby Function.)
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Rev. 3.00 May 15, 2007 Page 283 of 516
REJ09B0152-0300