HD64F38602R Datasheet, PDF (237/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 12 Watchdog Timer
12.2.2 Timer Control/Status Register WD2 (TCSRWD2)
TCSRWD2 performs the TCSRWD2 write control, mode switching, and interrupt control.
TCSRWD2 must be rewritten by using the MOV instruction. The bit manipulation instruction
cannot be used to change the setting value.
Initial
Bit
Bit Name Value R/W Description
7
OVF
0
R/(W)*¹ Overflow Flag
Indicates that TCWD has overflowed (changes from H'FF
to H'00).
[Setting condition]
When TCWD overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, this bit is cleared automatically by
the internal reset after it has been set.
[Clearing condition]
• When TCSRWD2 is read when OVF = 1, then 0 is
written to OVF
6
B5WI
1
R/(W)*² Bit 5 Write Inhibit
The WT/IT bit can be written only when the write value of
the B5WI bit is 0. This bit is always read as 1.
5
WT/IT
0
R/(W)*³ Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Watchdog timer mode
1: Interval timer mode
4
B3WI
1
R/(W)*² Bit 3 Write Inhibit
The IEOVF bit can be written only when the write value of
the B3WI bit is 0. This bit is always read as 1.
3
IEOVF 0
R/(W)*³ Overflow Interrupt Enable
Enables or disables an overflow interrupt request in
interval timer mode.
0: Disables an overflow interrupt
1: Enables an overflow interrupt
Rev. 3.00 May 15, 2007 Page 205 of 518
REJ09B0152-0300