HD64F38602R Datasheet, PDF (293/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.4.4 Serial Data Reception
Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
• Parity check
The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or
even) set in bit PM in the serial mode register (SMR).
• Stop bit check
The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred
from RSR to RDR.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI3 interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI3 interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI3 interrupt request is
generated. Continuous reception is possible because the RXI3 interrupt routine reads the
receive data transferred to RDR before reception of the next receive data has been completed.
Rev. 3.00 May 15, 2007 Page 261 of 518
REJ09B0152-0300