HD64F38602R Datasheet, PDF (304/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
14.6.1 Transmission
During transmission, the output signals from the SCI3 (UART frames) are converted to IR frames
using the IrDA interface (see figure 14.16).
For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is
output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in
IrCR.
According to the standard, the high-level pulse width is defined to be 1.41 µs at minimum and
(3/16 + 2.5%) × bit rate or (3/16 × bit rate) +1.08 µs at maximum. For example, when the
frequency of system clock φ is 10 MHz, being equal to or greater than 1.41 µs, the high-level pulse
width at minimum can be specified as 1.6 µs.
For serial data of level 1, no pulses are output.
Start
bit
UART frame
Data
Stop
bit
0
1
0
1
0
0
1
1
0
1
Transmission
Start
bit
01
IR frame
Reception
Data
01
0
01
1
Stop
bit
01
Bit
cycle
Pulse width is 1.6 µs to
3/16 bit cycle
Figure 14.16 IrDA Transmission and Reception
Rev. 3.00 May 15, 2007 Page 272 of 516
REJ09B0152-0300