HD64F38602R Datasheet, PDF (82/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.4.4 Interrupt Flag Register 1 (IRR1)
IRR1 indicates the IRQAEC, IRQ1, and IRQ0 interrupt request status.
Initial
Bit
Bit Name Value R/W Description
7 to 3 
All 0

Reserved
The write value should always be 0.
2
IRREC2 0
R/(W)* IRQAEC Interrupt Request Flag
[Setting condition]
When the P12 pin is set to the IRQAEC/AECPWM pin
and the specified edge is detected as the pin state
[Clearing condition]
When 0 is written to this bit
1
IRRI1
0
R/(W)* IRQ1 Interrupt Request Flag
[Setting condition]
When the IRQ1 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
0
IRRI0
0
R/(W)* IRQ0 Interrupt Request Flag
[Setting condition]
When the IRQ0 pin is set as the interrupt input pin and
the specified edge is detected
[Clearing condition]
When 0 is written to this bit
Note: * Only 0 can be written to clear the flag.
Rev. 3.00 May 15, 2007 Page 50 of 516
REJ09B0152-0300