HD64F38602R Datasheet, PDF (67/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 2 CPU
Reset state
Reset cleared
Reset occurs
Exception-handling state
Reset
occurs
Reset
occurs
Interrupt
source
Interrupt
source
Exception-
handling
complete
Program halt state
Program execution state
SLEEP instruction executed
Figure 2.12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4 or
R4L, which starts from the address indicated by R5, to the address indicated by R6. Set R4, R4L,
and R6 so that the end address of the destination address (value of R6 + R4L or R6 + R4) does not
exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution).
Rev. 3.00 May 15, 2007 Page 35 of 516
REJ09B0152-0300