HD64F38602R Datasheet, PDF (307/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 14 Serial Communication Interface 3 (SCI3, IrDA)
These interrupts are shown in table 14.14.
Table 14.14 Transmit/Receive Interrupts
Interrupt
RXI3
TXI3
TEI31
Flags
RDRF
RIE
TDRE
TIE
TEND
TEIE
Interrupt Request Conditions
Notes
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, an
RXI3 is enabled and an interrupt is
requested. (See figure 14.17 (a).)
The RXI3 interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by repeating
the above operations until reception of the
next RSR data is completed.
When TSR is found to be empty (on
The TXI3 interrupt routine writes the next
completion of the previous transmission) transmit data to TDR and clears bit TDRE
and the transmit data placed in TDR is to 0. Continuous transmission can be
transferred to TSR, bit TDRE is set to 1. performed by repeating the above
If bit TIE is set to 1 at this time, a TXI3 is operations until the data transferred to
enabled and an interrupt is requested. TSR has been transmitted.
(See figure 14.17 (b).)
When the last bit of the character in TSR A TEI3 indicates that the next transmit
is transmitted, if bit TDRE is set to 1, bit data has not been written to TDR when
TEND is set to 1. If bit TEIE is set to 1 at the last bit of the transmit character in
this time, a TEI3 is enabled and an
TSR is transmitted.
interrupt is requested. (See figure 14.17
(c).)
Rev. 3.00 May 15, 2007 Page 275 of 518
REJ09B0152-0300