HD64F38602R Datasheet, PDF (259/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
13.4.5 Operation of Clock Input Enable/Disable Function
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by the event counter PWM output, IECPWM when ECPWME in AEGSR is 1.
As this function forcibly terminates the clock input by each signal, a maximum error of one count
will occur depending on the IRQAEC or IECPWM timing. Figure 13.5 shows an example of the
operation.
Input event
IRQAEC or
IECPWM
Actually counted
clock source
Edge generated by clock return
Counter value
N
N+1
N+2
Clock stopped
N+3
N+4
N+5
N+6
Figure 13.5 Example of Clock Control Operation
Rev. 3.00 May 15, 2007 Page 227 of 516
REJ09B0152-0300