HD64F38602R Datasheet, PDF (347/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
Initial
Bit Bit Name Value R/W Description
5
MST
0
R/W Master/Slave Select
4
TRS
0
R/W Transmit/Receive Select
In master mode with the I²C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
After data receive has been started in slave receive
mode, when the first seven bits of the receive data
agree with the slave address that is set to SAR and the
eighth bit is 1, TRS is automatically set to 1. If an
overrun error occurs in master mode with the clock
synchronous serial format, MST is cleared to 0 and
slave receive mode is entered.
Operating modes are described below according to
MST and TRS combination. When clock synchronous
serial format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
3
CKS3
0
R/W Transfer Clock Select 3 to 0
2
CKS2
0
R/W These bits are valid only in master mode and should be
1
CKS1
0
R/W ^{set according to the necessary transfer rate (refer to}
table 16.2). These bit are used to specify the data setup
0
CKS0
0
R/W _{time in slave transmit mode. The data setup time is}
secured for 10tcyc when CKS3 = 0 and for 20tcyc when
CKS3 = 1.
Rev. 3.00 May 15, 2007 Page 315 of 516
REJ09B0152-0300