HD64F38602R Datasheet, PDF (110/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
5.1 Register Descriptions
The registers related to power-down modes are as follows.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2)
5.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Initial
Bit Bit Name Value R/W Description
7
SSBY
0
R/W Software Standby
Selects the mode to transit after the execution of the
SLEEP instruction.
0: A transition is made to sleep mode or subsleep
mode.
1: A transition is made to standby mode or watch mode.
For details, see table 5.2.
6
STS2
0
R/W Standby Timer Select 2 to 0
5
STS1
4
STS0
0
R/W Designate the time the CPU and peripheral modules
0
R/W ^{wait for stable clock operation after exiting from standby}
mode, subactive mode, or watch mode to active mode
or sleep mode due to an interrupt. The designation
should be made according to the operating frequency
so that the waiting time is at least equal to the
oscillation stabilization time. The relationship between
the specified value and the number of wait states is
shown in table 5.1.
When an external clock is to be used, the minimum
value (STS2 = 1, STS1 = 1, and STS0 = 1) is
recommended. When the on-chip oscillator is to be
used, the minimum value (STS2 = 1, STS1 = 1, and
STS0 = 1) is recommended. If a setting other than the
recommended value is made, operation may start
before the end of the waiting time.
Rev. 3.00 May 15, 2007 Page 78 of 516
REJ09B0152-0300