HD64F38602R Datasheet, PDF (26/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 21 Electrical Characteristics
Figure 21.1 Power Supply Voltage and Oscillation Frequency Range (1) ................................. 386
Figure 21.2 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 387
Figure 21.3 Power Supply Voltage and Operating Frequency Range (1)................................... 388
Figure 21.4 Power Supply Voltage and Operating Frequency Range (2)................................... 389
Figure 21.5 Power Supply Voltage and Operating Frequency Range (3)................................... 390
Figure 21.6 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (1) ................................................................................................... 391
Figure 21.7 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (2) ................................................................................................... 392
Figure 21.8 Power Supply Voltage and Oscillation Frequency Range (1) ................................. 412
Figure 21.9 Power Supply Voltage and Oscillation Frequency Range (2) ................................. 413
Figure 21.10 Power Supply Voltage and Operating Frequency Range (1)................................. 414
Figure 21.11 Power Supply Voltage and Operating Frequency Range (2)................................. 415
Figure 21.12 Power Supply Voltage and Operating Frequency Range (3)................................. 416
Figure 21.13 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (1).................................................................................................. 417
Figure 21.14 Analog Power Supply Voltage and Operating Frequency Range of
A/D Converter (2).................................................................................................. 418
Figure 21.15 Clock Input Timing ............................................................................................... 435
Figure 21.16 RES Low Width Timing........................................................................................ 435
Figure 21.17 Input Timing.......................................................................................................... 435
Figure 21.18 SCK3 Input Clock Timing .................................................................................... 435
Figure 21.19 SCI3 Input/Output Timing in Clock Synchronous Mode...................................... 436
Figure 21.20 SSU Input/Output Timing in Clock Synchronous Mode....................................... 436
Figure 21.21 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 1) ................................. 437
Figure 21.22 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Master, CPHS = 0) ................................. 437
Figure 21.23 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 1) ................................... 438
Figure 21.24 SSU Input/Output Timing
(Four-Line Bus Communication Mode, Slave, CPHS = 0) ................................... 438
Figure 21.25 I²C Bus Interface Input/Output Timing ................................................................. 439
Figure 21.26 Power-On Reset Circuit Reset Timing .................................................................. 439
Figure 21.27 Output Load Condition.......................................................................................... 440
Figure 21.28 Recommended Resonators .................................................................................... 440
Appendix
Figure B.1 (a) Port 1 Block Diagram (P12)................................................................................ 473
Figure B.1 (b) Port 1 Block Diagram (P11)................................................................................ 474
Rev. 3.00 May 15, 2007 Page xxvi of xxxii