HD64F38602R Datasheet, PDF (204/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
Figure 10.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
GRB
H'0200
H'0000
GRD H'0200
H'0450
H'0450
H'0520
H'0520
Time
GRB
H'0200
H'0450
H'0520
FTIOB
Figure 10.11 Buffer Operation Example (Output Compare)
Rev. 3.00 May 15, 2007 Page 172 of 516
REJ09B0152-0300