HD64F38602R Datasheet, PDF (352/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
Initial
Bit Bit Name Value R/W Description
2
BC2
0
R/W Bit Counter 2 to 0
1
BC1
0
BC0
0
R/W These bits specify the number of bits to be transferred
0
R/W ^{next. When read, the remaining number of transfer bits}
is indicated. With the I²C bus format, the data is
transferred with one addition acknowledge bit. Bit BC2
to BC0 settings should be made during an interval
between transfer frames. If bits BC2 to BC0 are set to a
value other than 000, the setting should be made while
the SCL pin is low. The value returns to 000 at the end
of a data transfer, including the acknowledge bit. With
the clock synchronous serial format, these bits should
not be modified.
I²C Bus Format
Clock Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bits
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
Rev. 3.00 May 15, 2007 Page 320 of 516
REJ09B0152-0300