HD64F38602R Datasheet, PDF (380/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 16 I²C Bus Interface 2 (IIC2)
16.7.4
Restriction on the Use of Bit Manipulation Instructions for MST and TRS
Setting in Multimaster Operation
In multimaster operation, if the master transmit is set with bit manipulation instructions in the
order from the MST bit to the TRS bit, the AL bit in the ICSR register will be set to 1 but the
master transmit mode (MST = 1, TRS = 1) may be set, depending on the arbitration lost timing. To
avoid this phenomenon, the following actions should be performed:
• In multimaster operation, use the MOV instruction to set bits MST and TRS.
• When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other
than MST = 0 and TRS = 0, set MST = 0 and TRS = 0 again.
16.7.5
Usage Note on Master Receive Mode
In master receive mode, SCL is fixed low on the falling edge of the 8th clock while the RDRF bit
is set to 1. When ICDRR is read around the falling edge of the 8th clock, the clock is only fixed
low in the 8th clock of the next round of data reception. The SCL is then released from its fixed
state without reading ICDRR and the 9th clock is output. As a result, some receive data is lost.
To avoid this phenomenon, the following actions should be performed:
• Read ICDRR in master receive mode before the rising edge of the 8th clock.
• Set RCVD to 1 in master receive mode and perform communication in units of one byte.
Rev. 3.00 May 15, 2007 Page 348 of 516
REJ09B0152-0300