HD64F38602R Datasheet, PDF (88/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.6.1 Interrupt Exception Handling Sequence
Figure 3.4 shows the interrupt exception handling sequence. The example shown is for the case
where the program area and stack area are in a 16-bit and 2-state access space.
Figure 3.4 Interrupt Exception Handling Sequence
Rev. 3.00 May 15, 2007 Page 56 of 516
REJ09B0152-0300