HD64F38602R Datasheet, PDF (191/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
Initial
Bit
Bit Name Value R/W Description
1
TOB
0
R/W Timer Output Level Setting B
Sets the output value of the FTIOB pin until the first
compare match B is generated.
0: Output value is 0*
1: Output value is 1*
0
TOA
0
R/W Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
[Legend] x: Don't care.
Note: * The change of the setting is immediately reflected in the output value.
10.3.3 Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Initial
Bit
Bit Name Value R/W
7
OVIE
0
R/W
6 to 4 
3
IMIED
All 1 
0
R/W
2
IMIEC
0
R/W
1
IMIEB
0
R/W
0
IMIEA
0
R/W
Description
Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by
OVF flag in TSRW is enabled.
Reserved
These bits are always read as 1.
Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
Rev. 3.00 May 15, 2007 Page 159 of 518
REJ09B0152-0300