HD64F38602R Datasheet, PDF (114/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
• CKSTPR2
Initial
Bit Bit Name Value R/W Description
7

0

Reserved
This bit is always read as 0 and cannot be modified.
6
TWCKSTP 0
R/W Timer W Module Standby
Timer W enters standby mode when this bit is cleared
to 0.
5
IICCKSTP 0
R/W IIC2 Module Standby
The IIC2 enters standby mode when this bit is cleared
to 0.
4
SSUCKSTP 0
R/W SSU Module Standby
The SSU enters standby mode when this bit is cleared
to 0.
3
AECCKSTP 0
R/W Asynchronous Event Counter Module Standby
The asynchronous event counter enters standby mode
when this bit is cleared to 0.
2
WDCKSTP 1
R/W*³ Watchdog Timer Module Standby
The watchdog timer enters standby mode when this bit
is cleared to 0.
1
COMPCKSTP 0
R/W Comparator Module Standby
The comparators enter standby mode when this bit is
cleared to 0.
0

0

Reserved
This bit is always read as 0 and cannot be modified.
Notes: 1. When the SCI3 module standby is set, all registers in the SCI3 enter the reset state.
2. When using the on-chip emulator, set this bit to 1.
3. This bit is valid when the WDON bit in TCSRW is 0. If this bit is cleared to 0 while the
WDON bit is set to 1 (while the watchdog timer is operating), this bit is cleared to 0.
However, the watchdog timer does not enter module standby mode and continues
operating. When the WDON bit is cleared to 0 by software, this bit is valid and the
watchdog timer enters module standby mode.
Rev. 3.00 May 15, 2007 Page 82 of 516
REJ09B0152-0300