HD64F38602R Datasheet, PDF (529/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Item
4.5.1 Note on Resonators and
Resonator Circuits
4.5.3 Definition of Oscillation
Stabilization Wait Time
Figure 4.12 Oscillation
Stabilization Wait Time
Page Revisions (See Manual for Details)
72 Modified
Resonator characteristics are closely related to board
design. Therefore, resonators should be assigned after
being carefully evaluated by the user in the masked
ROM version and flash memory version, with referring
to the examples shown in this section.
74 The description in this section is modified.
75 Modified
Oscillation waveform
(OSC2)
4.5.5 Note on the Oscillation
76
Stabilization of Resonators
4.5.6 Note on Using Power-On 76
Reset
Section 5 Power-Down Modes 81
5.1.3 Clock Halt Registers 1 and
2 (CKSTPR1 and CKSTPR2)
• CKSTPR2
Table 5.3 Internal State in Each 86
Operating Mode
System clock (φ)
Oscillation
start time
Wait time
Operating mode
Standby mode,
watch mode,
or subactive
mode
Oscillation stabilization wait time
Interrupt accepted
The title modified
Active (high-speed) mode or
active (medium-speed) mode
Modified
The power-on reset circuit in this LSI adjusts the reset
clear time by the capacitor capacitance, which is
externally connected to the RES pin. The external
capacitor capacitance should be adjusted to secure the
oscillation stabilization time before reset clearing. For
details, refer to section 19, Power-On Reset Circuit.
The note is modified.
Notes:
3. … When the watchdog timer stops operating and the
WDON bit is cleared to 0 by software, this bit is valid
and the watchdog timer enters module standby mode.
The note is modified.
Notes:
6. Functions if the 32.768-kHz RTC is selected as an
internal clock. Halted and retained otherwise.
Rev. 3.00 May 15, 2007 Page 497 of 516
REJ09B0152-0300