HD64F38602R Datasheet, PDF (81/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 3 Exception Handling
3.4.3 Interrupt Enable Register 2 (IENR2)
IENR2 enables the A/D converter, timer B1, and asynchronous event counter interrupts.
Initial
Bit
Bit Name Value
7

0
6
IENAD 0
5 to 3 
All 0
2
IENTB1 0
1

0
0
IENEC 0
R/W

R/W

R/W

R/W
Description
Reserved
The write value should always be 0.
A/D Converter Interrupt Request Enable
The A/D converter interrupt request is enabled when this
bit is set to 1.
Reserved
The write value should always be 0.
Timer B1 Interrupt Request Enable
The timer B1 interrupt request is enabled when this bit is
set to 1.
Reserved
The write value should always be 0.
Asynchronous Event Counter Interrupt Request Enable
The asynchronous event counter interrupt request is
enabled when this bit is set to 1.
Rev. 3.00 May 15, 2007 Page 49 of 516
REJ09B0152-0300