HD64F38602R Datasheet, PDF (120/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 5 Power-Down Modes
5.2.2 Standby Mode
In standby mode, the system clock oscillator stops, and the CPU and on-chip peripheral modules
stop functioning except for the WDT, asynchronous event counter, and comparators. However, as
long as the rated voltage is supplied, the contents of CPU registers and some on-chip peripheral
module registers are retained. On-chip RAM contents will be retained as long as the voltage set by
the RAM data retention voltage is provided. The I/O ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is
cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made
to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2.
Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by
the interrupt enable bit.
When a reset source is generated in standby mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the t_REL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
5.2.3 Watch Mode
In watch mode, the system clock oscillator and CPU operation stop, and on-chip peripheral
modules stop functioning except for the WDT, RTC, timer B1, asynchronous event counter, and
comparators. However, as long as the rated voltage is supplied, the contents of CPU registers,
some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain
their state before the transition.
Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and
interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is
made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on
the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is
made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt
exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable register.
When a reset source is generated in watch mode, the system clock oscillator starts. If a reset is
generated by the RES pin, it must be kept low until the system clock oscillator output stabilizes
and the t_REL period has elapsed. The CPU starts reset exception handling when the RES pin is
driven high.
Rev. 3.00 May 15, 2007 Page 88 of 516
REJ09B0152-0300