HD64F38602R Datasheet, PDF (145/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 6 ROM
Erase start
Set SWE bit to 1
Wait 1 µs
n=1
Set EBR1
Enable WDT
Set ESU bit to 1
Wait 100 µs
Set E bit to 1
Wait 10 ms
Clear E bit to 0
Wait 10 µs
Clear ESU bit to 0
Wait 10 µs
Disable WDT
Set EV bit to 1
Wait 20 µs
Set block start address to verifying address
Dummy write H'FF to verifying address
Wait 2 µs
*
Read verifying data
n←n+1
Increment address
No
No
Verifying data = all 1s ?
Yes
Last address of block ?
Yes
Clear EV bit to 0
Wait 4 µs
Clear EV bit to 0
Wait 4µs
No
All erase block erased ?
Yes
n ≤100 ?
Yes
Clear SWE bit to 0
No
Clear SWE bit to 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Note: *The RTS instruction must not be used during a period from dummy-writing of H'FF to a verifying address until reading verifying data
Figure 6.4 Erase/Erase-Verify Flowchart
Rev. 3.00 May 15, 2007 Page 113 of 518
REJ09B0152-0300