HD64F38602R Datasheet, PDF (212/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 10 Timer W
10.5.7 Timing of IMFA to IMFD Setting at Input Capture
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
10.22 shows the timing of the IMFA to IMFD flag setting at input capture.
φ
Input capture
signal
TCNT
N
GRA to GRD
N
IMFA to IMFD
IRRTW
Figure 10.22 Timing of IMFA to IMFD Flag Setting at Input Capture
10.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 10.23 shows the status flag clearing timing.
φ
Address
Write signal
TSRW write cycle
T1 T2
TSRW address
IMFA to IMFD
IRRTW
Figure 10.23 Timing of Status Flag Clearing by CPU
Rev. 3.00 May 15, 2007 Page 180 of 516
REJ09B0152-0300