HD64F38602R Datasheet, PDF (252/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 13 Asynchronous Event Counter (AEC)
13.3.5 Event Counter Control/Status Register (ECCSR)
ECCSR controls counter overflow detection, counter resetting, and count-up function.
Initial
Bit Bit Name Value R/W Description
7
OVH
0
R/W* Counter Overflow H
This is a status flag indicating that ECH has overflowed.
[Setting condition]
When ECH overflows from H’FF to H’00
[Clearing condition]
When this bit is written to 0 after reading OVH = 1
6
OVL
0
R/W* Counter Overflow L
This is a status flag indicating that ECL has overflowed.
[Setting condition]
When ECL overflows from H'FF to H'00 while CH2 is
set to 1
[Clearing condition]
When this bit is written to 0 after reading OVL = 1
5

0
R/W Reserved
Although this bit is readable/writable, only 0 should be
written to.
4
CH2
0
R/W Channel Select
Selects how ECH and ECL event counters are used
0: ECH and ECL are used together as a single-channel
16-bit event counter
1: ECH and ECL are used as two-channel 8-bit event
counter
3
CUEH
0
R/W Count-Up Enable H
Enables event clock input to ECH.
0: ECH event clock input is disabled (ECH value is
retained)
1: ECH event clock input is enabled
Rev. 3.00 May 15, 2007 Page 220 of 516
REJ09B0152-0300