HD64F38602R Datasheet, PDF (402/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 19 Power-On Reset Circuit
19.2 Operation
19.2.1 Power-On Reset Circuit
The operation timing of the power-on reset circuit is shown in figure 19.2. As the power supply
voltage rises, the capacitor, which is externally connected to the RES pin, is gradually charged
through the on-chip pull-up resistor (Rp). The low level of the RES pin is sent to the LSI and the
whole LSI is reset. When the level of the RES pin reaches to the predetermined level, a voltage
detection circuit detects it. Then a 3-bit counter starts counting up. When the 3-bit counter counts
φ for 8 times, an overflow signal is generated and an internal reset signal is negated.
The capacitance (C_RES) which is connected to the RES pin can be computed using the following
formula; where the RES rising time is t. For the on-chip resistor (Rp), see section 21, Electrical
Characteristics. The power supply rising time (t_vtr) should be shorter than half the RES rising
time (t). The RES rising time (t) is also should be longer than the oscillation stabilization time
(trc).
C_RES =
t
(t > trc, t > t_vtr × 2)
Rp
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
t_vtr
Vcc
RES
t_vtr × 2
V_rst
Internal reset
signal
t_cr
t_out (eight states)
Figure 19.2 Power-On Reset Circuit Operation Timing
Rev. 3.00 May 15, 2007 Page 370 of 516
REJ09B0152-0300