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HD64F38602R Datasheet, PDF (343/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer
Section 16 I2C Bus Interface 2 (IIC2)
Section 16 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The configuration of the registers that control the I2C bus differs partly from
the Philips configuration, however. Figure 16.1 shows a block diagram of the I2C bus interface 2.
Figure 16.2 shows an example of I/O pin connections to external circuits.
16.1 Features
• Selection of I2C format or clock synchronous serial format
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (The IIC2 is halted as the initial value. For details, refer to section 5.4, Module
Standby Function.)
I2C bus format
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• Direct bus drive
Two pins, SCL and SDA pins, function as CMOS outputs in normal operation (when the
port/serial function is selected) and NMOS outputs when the bus drive function is selected.
Clock synchronous format
• Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
Rev. 3.00 May 15, 2007 Page 311 of 516
REJ09B0152-0300