HD64F38602R Datasheet, PDF (320/552 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 15 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W Description
6
SSUMS 0
R/W SSU Mode Select
Selects which combination of the serial data input pin
and serial data output pin is used.
For details, refer to section 15.4.3, Relationship between
Data Input/Output and Shift Register.
0: Clocked synchronous communication mode
Data input: SSI pin, Data output: SSO pin
1: Four-line bus communication mode
When MSS = 1 and BIDE = 0 in SSCRH:
Data input: SSI pin, Data output: SSO pin
When MSS = 0 and BIDE = 0 in SSCRH:
Data input: SSO pin, Data output: SSI pin
When BIDE = 1 in SSCRH:
Data input and output: SSO pin
5
SRES
0
R/W Software Reset
When this bit is set to 1, the SSU internal sequencer is
forcibly reset. Then this bit is automatically cleared. The
register value in the SSU is retained.
4
SCKOS 0
R/W SSCK Pin Open-Drain Output Select
Selects whether the SSCK pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output
3
CSOS
0
R/W SCS Pin Open-Drain Output Select
Selects whether the SCS pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output
2 to 0 
All 0

Reserved
These bits are always read as 0.
Rev. 3.00 May 15, 2007 Page 288 of 516
REJ09B0152-0300